1. Field of the Invention
This disclosure relates to a semiconductor memory device, and more particularly, to a data output circuit in a combined single data rate/double data rate (SDR/DDR) synchronous semiconductor memory device.
2. Description of the Related Art
In general, synchronous semiconductor memory devices operate in an SDR mode where one bit of data is input/output for each data input/output pin during one clock cycle. However, in order to improve a data input/output rate, semiconductor memory devices that operate in a DDR where two bits of data are input/output for each data input/output pin during one clock cycle have been used.
A semiconductor memory device includes data output buffers, each of which is assigned with a data pin and includes a data output buffer and a data output driver, in order to externally output internal data, which are read from memory cells.
In conventional combined SDR/DDR semiconductor memory devices, since all data output buffers cannot be used as combined SDR/DDR data output buffers, the number of data output buffers increases and the efficiency of the data output buffers deteriorates.
FIG. 1 is a block diagram illustrating a data output circuit in a conventional combined SDR/DDR semiconductor memory device.
Referring to FIG. 1, the data output circuit includes a data output buffer 100 and a data output driver 200. Here, the data output buffer 100 includes four data latches 111 through 114 and two drivers 121 and 122.
It is assumed that the semiconductor memory device is operated in a DDR mode. In this case, the first and third data latches 111 and 113 latch even data D_E in response to an even clock CLK_E and convert the level of the latched data to output the data. Thus, the first and third data latches 111 and 113 latch the data to be output at the rising edge of a clock, and the second and fourth latches 112 and 114 latch the data to be output at the falling edge of the clock.
The drivers 121 and 122 drive the data received from the data latches 111 through 114 to output a pull-up control signal PB and a pull-down control signal NB.
The data output driver 200 includes a pull-up transistor PM1 and a pull-down transistor NM1.
Here, the pull-up transistor PM1 is formed of a PMOS transistor, and the pull-down transistor NM1 is formed of an NMOS transistor. The pull-up transistor PM1 and the pull-down transistor NM1 are gated in response to the pull-up control signal PB and the pull-down control signal NB, respectively, which are output from the data output buffer 100. The pull-up transistor PM1 is turned on when the pull-up control signal PB is at a low level to output an output data DQ of a high level. The pull-down transistor NM1 is turned on when the pull-down control signal NB is at a high level to output the output data DQ of a low level.
Meanwhile, it is assumed that the semiconductor memory device is operated in the SDR mode. In this case, the second and fourth data latches 112 and 114 are not used. In other words, the first and third data latches 111 and 113 latch data D1 at the rising edge of a data output clock CLKDQ and convert the level of the latched data to output the data.
The drivers 121 and 122 drive the data received from the data latches 111 through 114 to output the pull-up control signal PB and the pull-down control signal NB as in the case of the DDR mode.
The data output driver 200 outputs the output data DQ to the outside in response to the pull-up control signal PB and the pull-down control signal NB.
As described above, the conventional data output buffer 100 latches and outputs one bit of data in the SDR mode and two bits of data in the DDR mode.
Thus, the semiconductor memory device of SDR X16, which has 16 input/output pins and operates in the SDR mode, requires 16 data output buffers. When such a semiconductor memory device operates in the X8 DDR mode, the semiconductor memory device requires 9 data output buffers including a data strobe signal DQS buffer, which is used only in the DDR mode.
Therefore, in the conventional semiconductor memory device, some of the data output buffers are used as combined SDR/DDR data output buffers; however, the remaining data output buffers, for example, half of the data output buffers, are used as dedicated SDR data output buffers. In other words, the conventional semiconductor memory device requires a dedicated SDR data output circuit, in addition to the combined SDR/DDR data output circuit of FIG. 1.
FIG. 2 is a circuit diagram illustrating a combined SDR/DDR data output circuit in the conventional SDR/DDR semiconductor memory device, and FIG. 3 is a circuit diagram illustrating a dedicated SDR data output circuit in the conventional SDR/DDR semiconductor memory device. The conventional data output circuits will be described later in comparison with a data output circuit according to the present invention.
As a result, the conventional SDR/DDR semiconductor memory device requires equal number of data output buffers to the number of data input/output pins, and half of the data output buffers are used as the dedicated SDR data output buffers and are not available in the DDR mode.
Embodiments of the invention address these and other disadvantages in the conventional art.